A continuing goal of the semiconductor industry is to maximize circuit density. One conventional approach is to provide more than one semiconductor die (or chip) in a single integrated circuit package. To this end, in various conventional designs, first and second integrated circuit die are mounted on opposite sides of a leadframe die paddle. In some of these designs, the leadframe must be flipped in order to make all necessary wire bonding connections, and wires are bonded to both the upper and lower surfaces of the leads. Bonding to both lead surfaces requires plating both lead surfaces (e.g. with silver). In some designs, the die paddle must be specially designed to provide adequate heat transfer during wire bonding. Some designs require a special interconnect circuit which wraps around from one side of the die paddle to the other side of the die paddle. Bond pads of the integrated circuit die on one side of the die paddle are connected to the interconnect circuit in order to render that integrated circuit die electrically accessible from the other side of the die paddle.
It can be seen from the foregoing discussion that the conventional technique of mounting integrated circuit die on opposite sides of a leadframe die paddle adds complications to the design and production process.
FIG. 1 illustrates another conventional technique of providing more than one integrated circuit die in a single integrated circuit package. In FIG. 1, a spacer/interposer (such as a semiconductor substrate) is interposed between first and second integrated circuit die, one of which is mounted on the die paddle 11. The upper, active circuit areas of both integrated circuit die are wire bonded to the sets of leads 12 and 13. The existence of the spacer/interposer causes the arrangement of FIG. 1 to occupy more space than do the aforementioned arrangements wherein the integrated circuit die are mounted on opposite sides of the die paddle. Also, the arrangement of FIG. 1 introduces a mismatch in the coefficient of thermal expansion (CTE). Accordingly, the downset of the die paddle 11 with respect to the lead sets 12 and 13 is typically provided to compensate for this CTE mismatch.
It is desirable in view of the foregoing to provide for multichip packaging designs which can overcome the aforementioned disadvantages associated with various conventional approaches.